Invention Grant
- Patent Title: Patterning method for fabrication of a semiconductor device
- Patent Title (中): 用于制造半导体器件的图案化方法
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Application No.: US13307079Application Date: 2011-11-30
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Publication No.: US08592302B2Publication Date: 2013-11-26
- Inventor: Erik P. Geiss , Peter Baars
- Applicant: Erik P. Geiss , Peter Baars
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
A patterning method is provided for fabrication of a semiconductor device structure having conductive contact elements, an interlayer dielectric material overlying the contact elements, an organic planarization layer overlying the interlayer dielectric material, an antireflective coating material overlying the organic planarization layer, and a photoresist material overlying the antireflective coating material. The method creates a patterned photoresist layer from the photoresist material to define oversized openings corresponding to respective conductive contact elements. The antireflective coating is etched using the patterned photoresist as an etch mask. A liner material is deposited overlying the patterned antireflective coating layer. The liner material is etched to create sidewall features, which are used as a portion of an etch mask to form contact recesses for the conductive contact elements.
Public/Granted literature
- US20130137269A1 PATTERNING METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE Public/Granted day:2013-05-30
Information query
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