Invention Grant
US08592308B2 Silicided device with shallow impurity regions at interface between silicide and stressed liner
失效
在硅化物和应力衬里之间的界面具有浅杂质区的硅化器件
- Patent Title: Silicided device with shallow impurity regions at interface between silicide and stressed liner
- Patent Title (中): 在硅化物和应力衬里之间的界面具有浅杂质区的硅化器件
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Application No.: US13186587Application Date: 2011-07-20
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Publication No.: US08592308B2Publication Date: 2013-11-26
- Inventor: Javier Ayala , Christian Lavoie , Ahmet S. Ozcan
- Applicant: Javier Ayala , Christian Lavoie , Ahmet S. Ozcan
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Yuanmin Cai
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
A method of forming a semiconductor device includes forming a silicide contact region of a field effect transistor (FET); forming a shallow impurity region in a top surface of the silicide contact region; and forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.
Public/Granted literature
- US20130020616A1 SILICIDED DEVICE WITH SHALLOW IMPURITY REGIONS AT INTERFACE BETWEEN SILICIDE AND STRESSED LINER Public/Granted day:2013-01-24
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