Invention Grant
- Patent Title: Pseudo buried layer and manufacturing method of the same, deep hole contact and bipolar transistor
- Patent Title (中): 伪埋层及其制造方法相同,深孔接触和双极晶体管
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Application No.: US13227387Application Date: 2011-09-07
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Publication No.: US08592870B2Publication Date: 2013-11-26
- Inventor: Donghua Liu , Wensheng Qian
- Applicant: Donghua Liu , Wensheng Qian
- Applicant Address: CN Shanghai
- Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
- Current Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
- Current Assignee Address: CN Shanghai
- Agency: Blakely Sokoloff Taylor & Zafman
- Priority: CN201010275532 20100908
- Main IPC: H01L31/0328
- IPC: H01L31/0328 ; H01L31/0336 ; H01L31/072 ; H01L31/109 ; H01L29/167 ; H01L29/207 ; H01L29/227 ; H01L31/0288

Abstract:
The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices.
Public/Granted literature
- US20120056247A1 PSEUDO BURIED LAYER AND MANUFACTURING METHOD OF THE SAME, DEEP HOLE CONTACT AND BIPOLAR TRANSISTOR Public/Granted day:2012-03-08
Information query
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