Invention Grant
- Patent Title: Coupling well structure for improving HVMOS performance
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Application No.: US13280035Application Date: 2011-10-24
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Publication No.: US08592923B2Publication Date: 2013-11-26
- Inventor: Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
- Applicant: Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L29/66
- IPC: H01L29/66

Abstract:
A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
Public/Granted literature
- US20120037987A1 Coupling Well Structure for Improving HVMOS Performance Public/Granted day:2012-02-16
Information query
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