Invention Grant
- Patent Title: Semiconductor device including gate electrode having a laminate structure and a plug electrically connected thereto
- Patent Title (中): 半导体装置包括具有层叠结构的栅电极和与其电连接的插头
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Application No.: US13470372Application Date: 2012-05-14
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Publication No.: US08592924B2Publication Date: 2013-11-26
- Inventor: Yoshinori Tsuchiya , Masato Koyama
- Applicant: Yoshinori Tsuchiya , Masato Koyama
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Main IPC: H01L29/49
- IPC: H01L29/49

Abstract:
A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.
Public/Granted literature
- US20120223393A1 SEMICONDUCTOR DEVICE Public/Granted day:2012-09-06
Information query
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