Invention Grant
US08592992B2 Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
有权
用于3-D Fo-WLCSP的导电微孔阵列的垂直互连结构的半导体器件和方法
- Patent Title: Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
- Patent Title (中): 用于3-D Fo-WLCSP的导电微孔阵列的垂直互连结构的半导体器件和方法
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Application No.: US13326128Application Date: 2011-12-14
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Publication No.: US08592992B2Publication Date: 2013-11-26
- Inventor: Yaojian Lin , Kang Chen
- Applicant: Yaojian Lin , Kang Chen
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins & Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/522
- IPC: H01L23/522

Abstract:
A semiconductor device has a semiconductor die. An encapsulant is formed over the semiconductor die. A conductive micro via array is formed over the encapsulant outside a footprint of the semiconductor die. A first through-mold-hole having a step-through-hole structure is formed through the encapsulant to expose the conductive micro via array. In one embodiment, forming the conductive micro via array further includes forming an insulating layer over the encapsulant and the semiconductor die, forming a micro via array through the insulating layer outside the footprint of the semiconductor die, and forming a conductive layer over the insulating layer. In another embodiment, forming the conductive micro via array further includes forming a conductive ring. In another embodiment, an insulating layer is formed over the semiconductor die for structural support, a build-up interconnect structure is formed over the semiconductor die, and a conductive interconnect structure is formed within the first through-mold-hole.
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