Invention Grant
US08592994B2 Semiconductor package, core layer material, buildup layer material, and sealing resin composition
有权
半导体封装,芯层材料,堆积层材料和密封树脂组合物
- Patent Title: Semiconductor package, core layer material, buildup layer material, and sealing resin composition
- Patent Title (中): 半导体封装,芯层材料,堆积层材料和密封树脂组合物
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Application No.: US12517551Application Date: 2007-12-05
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Publication No.: US08592994B2Publication Date: 2013-11-26
- Inventor: Kenya Tachibana , Masahiro Wada , Hitoshi Kawaguchi , Kensuke Nakamura
- Applicant: Kenya Tachibana , Masahiro Wada , Hitoshi Kawaguchi , Kensuke Nakamura
- Applicant Address: JP Tokyo
- Assignee: Sumitomo Bakelite Co., Ltd.
- Current Assignee: Sumitomo Bakelite Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Ditthavong Mori & Steiner, P.C.
- Priority: JP2006-328364 20061205
- International Application: PCT/JP2007/073896 WO 20071205
- International Announcement: WO2008/069343 WO 20080612
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A flip-chip semiconductor package includes a circuit board having a core layer and at least one buildup layer, a semiconductor device connected to the circuit board through a metal bump, and a cured member that is made of a sealing resin composition and enclosed between the semiconductor device and the circuit board. The coefficient of linear expansion at 25 to 75° C. of the cured member is 15 to 35 ppm/° C., the glass transition temperature of at least one buildup layer is 170° C. or more, and the coefficient of linear expansion of at 25 to 75° C. of the at least one buildup layer in the planar direction is 25 ppm or less. A highly reliable flip-chip semiconductor package, buildup layer material, core layer material, and sealing resin composition can be provided by preventing cracks and inhibiting delamination.
Public/Granted literature
- US20100032826A1 SEMICONDUCTOR PACKAGE, CORE LAYER MATERIAL, BUILDUP LAYER MATERIAL, AND SEALING RESIN COMPOSITION Public/Granted day:2010-02-11
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