Invention Grant
- Patent Title: CMOS logic circuit
- Patent Title (中): CMOS逻辑电路
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Application No.: US13423485Application Date: 2012-03-19
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Publication No.: US08593178B2Publication Date: 2013-11-26
- Inventor: Hiroyuki Abe , Hironori Nagasawa
- Applicant: Hiroyuki Abe , Hironori Nagasawa
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Posz Law Group, PLC
- Priority: JP2011-177860 20110816
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H03K19/00 ; H03K19/091
Abstract:
A CMOS logic circuit includes a resistive element that is connected to a first voltage line at a first end thereof. The CMOS logic circuit includes a first inverter circuit having a first MOS transistor and a second MOS transistor. The CMOS logic circuit includes a second inverter circuit having a third MOS transistor and a fourth MOS transistor. The CMOS logic circuit includes a fifth MOS transistor that is connected in parallel with the resistive element between the first voltage line and the first end of the first MOS transistor and the gate of which is connected to the second end of the third MOS transistor. The CMOS logic circuit includes a sixth MOS transistor that is connected between the first voltage line and the first output terminal.
Public/Granted literature
- US20130043906A1 CMOS LOGIC CIRCUIT Public/Granted day:2013-02-21
Information query
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