Invention Grant
- Patent Title: Voltage generation circuit which is capable of reducing circuit area
- Patent Title (中): 能够减少电路面积的电压产生电路
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Application No.: US13239948Application Date: 2011-09-22
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Publication No.: US08593874B2Publication Date: 2013-11-26
- Inventor: Tatsuro Midorikawa
- Applicant: Tatsuro Midorikawa
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-245284 20101101
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/04 ; G11C5/14

Abstract:
According to one embodiment, a voltage generation circuit includes a first boost circuit, a first output circuit, a rectifying circuit, a second output circuit, and a detection circuit. The first boost circuit outputs a first voltage in first and second operation modes. The first output circuit is connected to the first boost circuit, and outputs the first voltage as a second voltage in the first operation mode. The rectifying circuit is connected to the first boost circuit, and outputs a third voltage which is lower than the first voltage in the first operation mode. The second output circuit short-circuits the rectifying circuit in the second operation mode, and outputs the first voltage as a fourth voltage. The detection circuit detects the second and fourth voltages which are supplied from the first and second output circuits.
Public/Granted literature
- US20120106255A1 VOLTAGE GENERATION CIRCUIT WHICH IS CAPABLE OF REDUCING CIRCUIT AREA Public/Granted day:2012-05-03
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