Invention Grant
- Patent Title: Semiconductor device and test method thereof
- Patent Title (中): 半导体器件及其测试方法
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Application No.: US13137969Application Date: 2011-09-22
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Publication No.: US08593891B2Publication Date: 2013-11-26
- Inventor: Naohisa Nishioka
- Applicant: Naohisa Nishioka
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2010-230332 20101013
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
A semiconductor device includes a plurality of core chips to which chip identification information different from each other is allocated and an interface chip are layered, the plurality of core chips are commonly connected to the interface chip through a first current path including at least a through silicon via, the interface chip serially supplies an enable signal to the plurality of core chips through the first current path, and the plurality of core chips are activated based on a logic level of a bit corresponding to the chip identification information among a plurality of bits configuring the enable signal. The present invention can reduce the number of through silicon vias required to supply an enable signal.
Public/Granted literature
- US20120092943A1 Semiconductor device and test method thereof Public/Granted day:2012-04-19
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