An apparatus having first and second circuits is disclosed. The first circuit may be disposed on a first side of a bus and configured to store thresholds in a first memory. Each threshold generally represents a respective one of a plurality of regular bit patterns in first data. The first circuit may also be configured to generate second data by representing each respective first data as (i) an index to one of the thresholds and (ii) a difference between the one threshold and the respective first data. A width of the bus may be narrower than the respective first data. The second circuit may be disposed on a second side of the bus and configured to (i) store the thresholds and a plurality of items in a second memory and (ii) reconstruct the first data by adding the respective thresholds to the second data in response to the items.