Invention Grant
US08595429B2 Wide input/output memory with low density, low latency and high density, high latency blocks
有权
宽输入/输出存储器，具有低密度，低延迟和高密度，高延迟模块
- Patent Title: Wide input/output memory with low density, low latency and high density, high latency blocks
- Patent Title (中): 宽输入/输出存储器，具有低密度，低延迟和高密度，高延迟模块
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Application No.: US12862094Application Date: 2010-08-24
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Publication No.: US08595429B2Publication Date: 2013-11-26
- Inventor: Shiqun Gu , Matthew M. Nowak , Anand Srinivasan
- Applicant: Shiqun Gu , Matthew M. Nowak , Anand Srinivasan
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Michelle S. Gallardo
- Main IPC: G06F12/00
- IPC: G06F12/00
Abstract:
External memory having a high density, high latency memory block; and a low density, low latency memory block. The two memory blocks may be separately accessed by one or more processing functional units. The access may be a direct memory access, or by way of a bus or fabric switch. Through-die vias may connect the external memory to a die comprising the one or more processing functional units.
Public/Granted literature
- US20120054422A1 Wide Input/Output Memory with Low Density, Low Latency and High Density, High Latency Blocks Public/Granted day:2012-03-01
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