Some of the embodiments of the present disclosure provide apparatuses, systems, and methods for reducing the likelihood of cache line overlaps in a multi-processor system having a shared memory cache. A transformation function module coupled to the shared memory cache is configured to transform an index associated with a cache operation associated with a processor of the plurality of processors using a transformation function to generate a transformed index. In embodiments, groups of one or more processors have different or unique transformation functions associated with them in order to decrease the tendency or likelihood of their respective cache lines in the shared memory cache to overlap. Other embodiments are also described and claimed.