Invention Grant
- Patent Title: Rate verification of an incoming serial alignment sequence
- Patent Title (中): 输入串行对齐序列的速率验证
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Application No.: US13014615Application Date: 2011-01-26
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Publication No.: US08595536B2Publication Date: 2013-11-26
- Inventor: Vincent E. Von Bokern , Serge Bedwani
- Applicant: Vincent E. Von Bokern , Serge Bedwani
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06F1/12
- IPC: G06F1/12 ; G06F13/42 ; H04L5/00 ; H04L7/00 ; G06F1/00 ; G11B15/18 ; G11B17/00 ; G11B19/02
Abstract:
A technique for rate verification of an incoming serial alignment sequence includes receiving an incoming serial stream. A determination is then made as to whether an align sequence is recognized in the incoming serial stream. When an align sequence is recognized, a check is made to determine if an appropriate number of align primitives are received during a predetermined number of clock periods. If the number of received align primitives matches the predetermined number, then a rate-verified align detect signal is asserted.
Public/Granted literature
- US20110141605A1 RATE VERIFICATION OF AN INCOMING SERIAL ALIGNMENT SEQUENCE Public/Granted day:2011-06-16
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