Invention Grant
US08595541B2 Data processing modules requiring different average clock frequencies having a common clock and a clock gating circuit for deleting clock pulses applied to the modules at times consistent with data sourcing and sinking capabilities
有权
需要不同平均时钟频率的数据处理模块，具有公共时钟和时钟门控电路，用于在与数据采集和吸收能力相符的时候删除施加到模块的时钟脉冲
- Patent Title: Data processing modules requiring different average clock frequencies having a common clock and a clock gating circuit for deleting clock pulses applied to the modules at times consistent with data sourcing and sinking capabilities
- Patent Title (中): 需要不同平均时钟频率的数据处理模块，具有公共时钟和时钟门控电路，用于在与数据采集和吸收能力相符的时候删除施加到模块的时钟脉冲
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Application No.: US12215691Application Date: 2008-06-27
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Publication No.: US08595541B2Publication Date: 2013-11-26
- Inventor: Paul Rowland
- Applicant: Paul Rowland
- Applicant Address: GB Kings Langlet, Hartfordshire
- Assignee: Imagination Technologies, Ltd.
- Current Assignee: Imagination Technologies, Ltd.
- Current Assignee Address: GB Kings Langlet, Hartfordshire
- Agency: ArtesynIP, Inc.
- Agent Michael S. Garrabrants
- Priority: GB0712788 20070629
- Main IPC: G06F1/00
- IPC: G06F1/00 ; G06F13/24
Abstract:
A method and apparatus are provided for docking data processing modules, which require differing average clock frequencies, and for transferring data between the modules. This comprises a means for providing a common dock signal to modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the docking frequency required by each module. Clock pulses are applied to modules between which data is to be transferred at times consistent with the data transfer.
Public/Granted literature
- US20090019303A1 Clock frequency adjustment for semi-conductor devices Public/Granted day:2009-01-15
Information query
