Invention Grant
- Patent Title: Quasi-cyclic low-density parity-check codes
- Patent Title (中): 准循环低密度奇偶校验码
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Application No.: US13251180Application Date: 2011-09-30
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Publication No.: US08595589B2Publication Date: 2013-11-26
- Inventor: Jonathan Yedidia , Yige Wang
- Applicant: Jonathan Yedidia , Yige Wang
- Applicant Address: US MA Cambridge
- Assignee: Mitsubishi Electric Research Laboratories, Inc.
- Current Assignee: Mitsubishi Electric Research Laboratories, Inc.
- Current Assignee Address: US MA Cambridge
- Agent Dirk Brinkman; Gene Vinokur
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
A system and a method for determining a quasi-cyclic (QC) low-density parity-check (LDPC) code, such that the QC LDPC code has no trapping sets are disclosed. A set of matrices representing a family of QC LDPC codes are acquired, wherein each QC LDPC code is a tail-biting spatially-coupled code of girth not less than eight, and wherein each column of each matrix in the set has a weight not less than four. Based on a trapping set pattern, a matrix from the set of matrices is selected such that the matrix represents the QC LDPC code with no trapping sets. The matrix can be stored into a memory.
Public/Granted literature
- US20130086445A1 Quasi-Cyclic Low-Density Parity-Check Codes Public/Granted day:2013-04-04
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