Invention Grant
US08595734B2 Reduction of processing time when cache miss occurs 有权
减少缓存未命中时的处理时间

  • Patent Title: Reduction of processing time when cache miss occurs
  • Patent Title (中): 减少缓存未命中时的处理时间
  • Application No.: US13147973
    Application Date: 2010-02-25
  • Publication No.: US08595734B2
    Publication Date: 2013-11-26
  • Inventor: Kenji Kanemura
  • Applicant: Kenji Kanemura
  • Applicant Address: JP Tokyo
  • Assignee: NEC Corporation
  • Current Assignee: NEC Corporation
  • Current Assignee Address: JP Tokyo
  • Priority: JP2009-045875 20090227
  • International Application: PCT/JP2010/052987 WO 20100225
  • International Announcement: WO2010/098394 WO 20100902
  • Main IPC: G06F9/46
  • IPC: G06F9/46
Reduction of processing time when cache miss occurs
Abstract:
Communication performance of inter-process communication in enhanced for the entire program processing. A process allocation system is provided with a processor which executes a process including a process for performing mutual inter-process communication and holding a logical process placement system, and a process allocation module for allocating each process to the processor, wherein the process allocation module is provided with an inter-processor communication capacity acquisition module for acquiring the communication performance of inter-processor communication which the processor performs with other different processor, a module for specifying the dimensional direction in which the communication traffic of inter-process communication is high in the logical process placement system, and a module for determining a processor having a higher communication performance of inter-processor communication as the allocation destination of a process which is set in the dimensional direction of higher inter-process communication traffic.
Information query
Patent Agency Ranking
0/0