Invention Grant
- Patent Title: Method of manufacturing a semiconductor device
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Application No.: US12201546Application Date: 2008-08-29
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Publication No.: US08597427B2Publication Date: 2013-12-03
- Inventor: Satoru Okamoto
- Applicant: Satoru Okamoto
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Fish & Richardson P.C.
- Priority: JP2001-342212 20011107
- Main IPC: C30B21/02
- IPC: C30B21/02

Abstract:
A semiconductor device is provided which is constituted by semiconductor devices including a thin film transistor with a GOLD structure, the GOLD structure thin film transistor being such that: a semiconductor layer, a gate insulating film, and a gate electrode are formed in lamination from the side closer to a substrate; the gate electrode is constituted of a first-layer gate electrode and a second-layer gate electrode shorter in the size than the first-layer gate electrode; the first-layer gate electrode corresponding to the region exposed from the second-layer gate electrode is formed into a tapered shape so as to be thinner toward the end portion; a first impurity region is formed in the semiconductor layer corresponding to the region with the tapered shape; and a second impurity region having the same conductivity as the first impurity region is formed in the semiconductor layer corresponding to the outside of the first-layer gate electrode, which is characterized in that a dry etching process consisting of one step or two steps is applied to the formation of the gate electrode.
Public/Granted literature
- US20090004872A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE Public/Granted day:2009-01-01
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