Invention Grant
- Patent Title: Method for manufacturing twin bit structure cell with hafnium oxide and nano-crystalline silicon layer
- Patent Title (中): 用铪氧化物和纳米晶硅层制造双位结构电池的方法
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Application No.: US12978473Application Date: 2010-12-24
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Publication No.: US08598001B2Publication Date: 2013-12-03
- Inventor: Mieno Fumitake
- Applicant: Mieno Fumitake
- Applicant Address: CN Shanghai CN Beijing
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee Address: CN Shanghai CN Beijing
- Agency: Kilpatrick Townsend and Stockton LLP
- Priority: CN200910247494 20091229
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method and system for forming a non-volatile memory structure. The method provides a semiconductor substrate and forms a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying the gate dielectric layer. The method subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure and formation of a second silicon oxide layer overlying a surface region of the substrate. A hafnium oxide material is formed overlying the first and second silicon oxide layers and filling the undercut region. The hafnium oxide material has a nanocrystalline silicon material sandwiched between a first hafnium oxide layer and a second hafnium oxide layer. The hafnium oxide material is selectively etched while a portion of it is maintained in an insert region in a portion of the undercut region.
Public/Granted literature
- US20110156129A1 METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH HAFNIUM OXIDE AND NANO-CRYSTALLINE SILICON LAYER Public/Granted day:2011-06-30
Information query
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