Invention Grant
- Patent Title: Semiconductor integrated circuit chip and layout method for the same
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Application No.: US13888947Application Date: 2013-05-07
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Publication No.: US08598631B2Publication Date: 2013-12-03
- Inventor: Shiro Usami
- Applicant: Panasonic Corporation
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2009-108220 20090427
- Main IPC: H01L27/10
- IPC: H01L27/10

Abstract:
A semiconductor integrated circuit chip mounted on a substrate by flip chip bonding includes: a plurality of electrode pads; a corner portion of a flat periphery of an inner layer; a first linear region adjoining one side of the corner portion; a second linear region adjoining another side of the corner portion; and a third linear region adjoining a side of the first linear region opposite to the side adjoining the corner portion. A circuit core placeable region is provided in at least part of the corner portion and the first linear region. A plurality of IO cells connected to the electrode pads are arranged in the second and third linear regions. The IO cells in the second linear region are connected to the electrode pads arranged inwardly in n rows×n columns from a corner of the chip above the corner portion.
Public/Granted literature
- US20130240954A1 SEMICONDUCTOR INTEGRATED CIRCUIT CHIP AND LAYOUT METHOD FOR THE SAME Public/Granted day:2013-09-19
Information query
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