Invention Grant
US08598632B2 Integrated circuit having pitch reduced patterns relative to photoithography features
失效
具有相对于光刻特征的节距减小图案的集成电路
- Patent Title: Integrated circuit having pitch reduced patterns relative to photoithography features
- Patent Title (中): 具有相对于光刻特征的节距减小图案的集成电路
-
Application No.: US13530679Application Date: 2012-06-22
-
Publication No.: US08598632B2Publication Date: 2013-12-03
- Inventor: Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
- Applicant: Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
- Applicant Address: US NJ Jersey City
- Assignee: Round Rock Research LLC
- Current Assignee: Round Rock Research LLC
- Current Assignee Address: US NJ Jersey City
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L27/118
- IPC: H01L27/118
Abstract:
An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.
Public/Granted literature
- US20120256309A1 Integrated Circuit Having Pitch Reduced Patterns Relative To Photolithography Features Public/Granted day:2012-10-11
Information query
IPC分类:
