Invention Grant
- Patent Title: Bitwidth reduction in loop filters used for digital PLLS
- Patent Title (中): 用于数字PLLS的环路滤波器的带宽减少
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Application No.: US13664536Application Date: 2012-10-31
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Publication No.: US08598929B1Publication Date: 2013-12-03
- Inventor: Christian Wicpalek , Thomas Mayer
- Applicant: Christian Wicpalek , Thomas Mayer
- Applicant Address: DE Neubiberg
- Assignee: Intel Mobile Communications GmbH
- Current Assignee: Intel Mobile Communications GmbH
- Current Assignee Address: DE Neubiberg
- Agency: Eschweiler & Associates, LLC
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
The disclosed invention relates to a digital phase locked loop having a switchable digital loop filter configured to selectively operate at different levels of resolution. The digital phase locked loop has a phase frequency detector that determines a phase difference between a reference signal and a feedback signal and to convert the phase difference to a digital word. A digital loop filter filters the digital word to generate a control word. A bit shift network modifies the digital word in a manner that switches the resolution of the digital loop filter between two or more distinct resolution states that comprise a bit sequence located at different positions in the digital word. The two or more distinct resolution states allow the digital loop filter to provide a low resolution (high amplitude) for a settling state of operation and a high resolution (low amplitude) for a locked state of operation.
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