According to one embodiment, a device for synchronizing data output from two or more memory arrays that includes a plurality of sense circuits configured to be responsive to a clock signal. The device further includes a plurality of latches and a tracking circuit. The tracking circuit may be configured to produce a control signal responsive to the clock signal. The control signal may be operable to enable the plurality of latches. The tracking has an associated delay that is substantially the same as a delay associated with at least one of the plurality of sense circuits.