An arithmetic processing apparatus includes: a plurality of processing units connected in series to each other, wherein each of the processing units includes a limitation information setting section in which limitation information, which indicates the amount of arithmetic processing that each of the processing units is to process for data of each arithmetic processing unit, is set; an arithmetic section which executes arithmetic processing on the data of each arithmetic processing unit, according to the limitation information set in the limitation information setting section, by the same program between the plurality of processing units; and a memory in which processing data subjected to the arithmetic processing by the arithmetic section is stored.