Invention Grant
US08601302B2 Processor system in low power state retention mode with linear regulator off and switch regulator low in power management IC
有权
处理器系统处于低功率状态保持模式,线性稳压器关闭,开关稳压器电源管理IC低
- Patent Title: Processor system in low power state retention mode with linear regulator off and switch regulator low in power management IC
- Patent Title (中): 处理器系统处于低功率状态保持模式,线性稳压器关闭,开关稳压器电源管理IC低
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Application No.: US12488814Application Date: 2009-06-22
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Publication No.: US08601302B2Publication Date: 2013-12-03
- Inventor: Manish Lachwani , David Berbessou
- Applicant: Manish Lachwani , David Berbessou
- Applicant Address: US NV Reno
- Assignee: Amazon Technologies, Inc.
- Current Assignee: Amazon Technologies, Inc.
- Current Assignee Address: US NV Reno
- Agency: Lee & Hayes, PLLC
- Main IPC: G06F1/32
- IPC: G06F1/32

Abstract:
A quiescent state retention mode (QSRM) permits minimal power consumption and dissipation by an electronic device while idle without producing adverse latencies to users or causing system instability. Upon a call to enter the QSRM, processes may be frozen, clocks may be gated, switching regulators may be placed in low power mode, SDRAM may be placed into self-refresh mode, caches may be flushed, IRQs may be disabled, and the system waits for interrupt to wakeup. In the QSRM, powered components include the switching regulator configured to provide power to the processor is maintained in a low power mode while the SDRAM is placed in self-refresh.
Public/Granted literature
- US20100325457A1 Quiescent State Retention Mode for Processor Public/Granted day:2010-12-23
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