A system-on-chip includes first and second memories, a descrambler, and logic. The first memory stores firmware. A first portion of the firmware is scrambled and located at a predetermined address in the first memory. The second memory stores boot code for a processor. In response to the processor being booted, the boot code instructs the processor to read the first portion of the firmware from the predetermined address in the first memory. The descrambler is configured to create a descrambled value by descrambling the first portion of the firmware. The logic is configured to, in response to the descrambled value matching a predetermined authorization code, enable a test interface that allows a device external to the system-on-chip to access the processor through the test interface. The logic is further configured to, in response to the descrambled value not matching the predetermined authorization code, disable the test interface.