Invention Grant
- Patent Title: Method of circuit design yield analysis
- Patent Title (中): 电路设计产量分析方法
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Application No.: US13535709Application Date: 2012-06-28
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Publication No.: US08601416B2Publication Date: 2013-12-03
- Inventor: Chin-Cheng Kuo , Wei-Yi Hu , Jui-Feng Kuan , Yi-Kan Cheng
- Applicant: Chin-Cheng Kuo , Wei-Yi Hu , Jui-Feng Kuan , Yi-Kan Cheng
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Agent Steven E. Koffs
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method includes (a) generating a set of samples, each sample representing a respective set of semiconductor fabrication process variation values; (b) selecting a first subset of the set of samples based on a probability of the set of semiconductor fabrication process variation values corresponding to each sample; (c) estimating a yield measure for a semiconductor product based on relative sizes of the set of samples and the first subset, without performing a Monte Carlo simulation; and (d) outputting an indication that a design modification is appropriate, if the estimated yield measure is below a specification yield value.
Public/Granted literature
- US20130246986A1 METHOD OF CIRCUIT DESIGN YIELD ANALYSIS Public/Granted day:2013-09-19
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