Invention Grant
US08601427B2 Intergrated circuit having latch circuits and using delay to fetch data bits in synchronization with clock signals
有权
集成电路具有锁存电路并且使用延迟来与时钟信号同步地获取数据位
- Patent Title: Intergrated circuit having latch circuits and using delay to fetch data bits in synchronization with clock signals
- Patent Title (中): 集成电路具有锁存电路并且使用延迟来与时钟信号同步地获取数据位
-
Application No.: US13362414Application Date: 2012-01-31
-
Publication No.: US08601427B2Publication Date: 2013-12-03
- Inventor: Masakuni Kawagoe
- Applicant: Masakuni Kawagoe
- Applicant Address: JP Tokyo
- Assignee: Lapis Semiconductor Co., Ltd.
- Current Assignee: Lapis Semiconductor Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Volentine & Whitt, PLLC.
- Priority: JP2011-025807 20110209
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path.
Public/Granted literature
Information query
