Invention Grant
- Patent Title: Multiplier-free algorithms for sample-time and gain mismatch error estimation in a two-channel time-interleaved analog-to-digital converter
- Patent Title (中): 双通道时间交织模数转换器的采样时间和增益失配误差估计的无乘法算法
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Application No.: US13413764Application Date: 2012-03-07
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Publication No.: US08604952B2Publication Date: 2013-12-10
- Inventor: Sunder S. Kidambi , Brannon Harris
- Applicant: Sunder S. Kidambi , Brannon Harris
- Applicant Address: US CA Milpitas
- Assignee: Intersil Americas LLC
- Current Assignee: Intersil Americas LLC
- Current Assignee Address: US CA Milpitas
- Agency: Cessari and McKenna, LLP/Intersil
- Agent David J. Thibodeau
- Main IPC: H03M1/06
- IPC: H03M1/06

Abstract:
Techniques for the estimation of sample-time and gain mismatch errors in a two-channel time interleaved analog to digital converter that are devoid of any multiplication operation. In a sample-time mismatch error evaluation, the signs and the absolute values from the two ADCs are used to provide an estimate of the sample-time mismatch error. In a gain error estimation algorithm, the absolute values of the outputs from the two ADCs are subtracted and accumulated. The errors can then be corrected, in a preferred embodiment, using suitable adaptive sample time and gain correction techniques.
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