Invention Grant
US08604953B2 Calibrating timing, gain and bandwidth mismatch in interleaved ADCs
有权
校准交错ADC中的时序,增益和带宽不匹配
- Patent Title: Calibrating timing, gain and bandwidth mismatch in interleaved ADCs
- Patent Title (中): 校准交错ADC中的时序,增益和带宽不匹配
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Application No.: US13596626Application Date: 2012-08-28
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Publication No.: US08604953B2Publication Date: 2013-12-10
- Inventor: Ahmed Mohamed Abdelatty Ali
- Applicant: Ahmed Mohamed Abdelatty Ali
- Applicant Address: US MA Norwood
- Assignee: Analog Devices, Inc.
- Current Assignee: Analog Devices, Inc.
- Current Assignee Address: US MA Norwood
- Agency: Kenyon & Kenyon LLP
- Main IPC: H03M1/10
- IPC: H03M1/10

Abstract:
A method and a corresponding device for calibrating an interleaved analog-to-digital converter (ADC) involve injecting a randomly determined amount of dither into at least one of a flash component and a multiplying digital-to-analog converter (MDAC) in a selected channel in the ADC. A correlation procedure is performed to estimate, based on an overall ADC output, a gain experienced by the injected dither after propagating through the channel. The injection and the correlation procedure are repeated on at least one additional channel to estimate a gain for each at least one additional channel. The estimated gains of the selected channel and the at least one additional channel are then compared to determine a degree of mismatch between the selected channel and each at least one additional channel. At least one channel is calibrated as a function of the determined degree of mismatch.
Public/Granted literature
- US20130120175A1 CALIBRATING TIMING, GAIN AND BANDWIDTH MISMATCH IN INTERLEAVED ADCs Public/Granted day:2013-05-16
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