A transceiver system having a phase and frequency locked architecture is described. The transceiver system includes a clock and data recovery type receiver, a frequency divider and a transmitter. The clock and data recovery type receiver receives an external signal from a host unit and extracts the external signal to generate a clock signal and a data signal. The frequency divider is used to divide the frequency of the clock signal for generating a reference clock signal. The transmitter transmits output data content based on the reference clock signal.