Invention Grant
US08606556B2 Circuit-level validation of computer executable device/circuit simulators
失效
计算机可执行设备/电路模拟器的电路级验证
- Patent Title: Circuit-level validation of computer executable device/circuit simulators
- Patent Title (中): 计算机可执行设备/电路模拟器的电路级验证
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Application No.: US12685108Application Date: 2010-01-11
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Publication No.: US08606556B2Publication Date: 2013-12-10
- Inventor: Aditya Bansal , Pamela Castalino , Dallas M. Lea , Amith Singhee
- Applicant: Aditya Bansal , Pamela Castalino , Dallas M. Lea , Amith Singhee
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent George Sai-Halasz; Preston J. Young
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06G7/62

Abstract:
A method is disclosed for evaluating a model, characterized as being a computer executable device and circuit simulator. The method includes accepting measured parameters of devices, which devices are essentially identical with, or are actually from, a simulated circuit instance. The model is executed with adjusted input parameters to generate simulated values for properties of the circuit instance. These simulated values are compared with measured values of the same properties. The goodness of the model is determined based on the degree of direct, or statistical, agreement between the simulated and measured values.
Public/Granted literature
- US20110172979A1 CIRCUIT-LEVEL VALIDATION OF COMPUTER EXECUTABLE DEVICE/CIRCUIT SIMULATORS Public/Granted day:2011-07-14
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