Invention Grant
- Patent Title: Hardware device for processing the tasks of an algorithm in parallel
- Patent Title (中): 用于并行处理算法任务的硬件设备
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Application No.: US13365376Application Date: 2012-02-03
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Publication No.: US08607031B2Publication Date: 2013-12-10
- Inventor: Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
- Applicant: Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran & Cole, P.C.
- Agent Mark C. Vallone
- Priority: EP99480050 19990701
- Main IPC: G06F9/30
- IPC: G06F9/30

Abstract:
A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, includes a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units. A task interconnection logic means interconnect the task units for communicating actions from a source task unit to a destination task unit. Each of the task units includes a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action, and a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units.
Public/Granted literature
- US20120137110A1 HARDWARE DEVICE FOR PROCESSING THE TASKS OF AN ALGORITHM IN PARALLEL Public/Granted day:2012-05-31
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