Invention Grant
US08607109B2 Test circuitry including core output, expected response, and mask circuitry
有权
测试电路包括核心输出，预期响应和掩码电路
- Patent Title: Test circuitry including core output, expected response, and mask circuitry
- Patent Title (中): 测试电路包括核心输出，预期响应和掩码电路
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Application No.: US13909384Application Date: 2013-06-04
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Publication No.: US08607109B2Publication Date: 2013-12-10
- Inventor: Lee D. Whetsel
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R31/26
Abstract:
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
Public/Granted literature
- US20130275825A1 SEMICONDUCTOR TEST SYSTEM AND METHOD Public/Granted day:2013-10-17
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