Invention Grant
- Patent Title: Semiconductor device including latency counter
-
Application No.: US13317598Application Date: 2011-10-24
-
Publication No.: US08611177B2Publication Date: 2013-12-17
- Inventor: Hiroki Fujisawa
- Applicant: Hiroki Fujisawa
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2010-257323 20101117
- Main IPC: G11C8/18
- IPC: G11C8/18

Abstract:
For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since the number of bits in control information, which is used to set a latency, is smaller than the types of settable latency as a result, it is possible to reduce wiring density.
Public/Granted literature
- US20120120754A1 Semiconductor device including latency counter Public/Granted day:2012-05-17
Information query