Invention Grant
US08612797B2 Systems and methods of selectively managing errors in memory modules
有权
选择性地管理存储器模块中的错误的系统和方法
- Patent Title: Systems and methods of selectively managing errors in memory modules
- Patent Title (中): 选择性地管理存储器模块中的错误的系统和方法
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Application No.: US11394585Application Date: 2006-03-31
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Publication No.: US08612797B2Publication Date: 2013-12-17
- Inventor: Larry J. Thayer , Andrew C. Walton , Mike H. Cogdill , George Krejci
- Applicant: Larry J. Thayer , Andrew C. Walton , Mike H. Cogdill , George Krejci
- Applicant Address: US TX Houston
- Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee Address: US TX Houston
- Main IPC: G06F11/07
- IPC: G06F11/07

Abstract:
System and methods of selectively managing errors in memory modules. In an exemplary implementation, a method may include monitoring for persistent errors in the memory modules. The methods may also include mapping at least a portion of the memory modules to a spare memory cache only to obviate persistent errors. The method may also include initiating memory erasure on at least a portion of the memory modules only if insufficient cache lines are available in the spare memory cache.
Public/Granted literature
- US20070234112A1 Systems and methods of selectively managing errors in memory modules Public/Granted day:2007-10-04
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