Invention Grant
- Patent Title: Wiring method for semiconductor integrated circuit, semiconductor-circuit wiring apparatus and semiconductor integrated circuit
- Patent Title (中): 半导体集成电路的接线方法,半导体电路布线装置和半导体集成电路
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Application No.: US13233996Application Date: 2011-09-15
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Publication No.: US08614515B2Publication Date: 2013-12-24
- Inventor: Tetsuaki Utsumi
- Applicant: Tetsuaki Utsumi
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Knobbe, Martens, Olson & Bear LLP
- Priority: JP2010-294025 20101228
- Main IPC: H01L29/40
- IPC: H01L29/40

Abstract:
A wiring method for a semiconductor integrated circuit has the steps of, separately from a first layer on which a first signal wiring pattern is mainly formed, laying out a first power-supply wiring pattern on a second layer so that a plurality of rows of the first power-supply wiring pattern are regularly arranged with vacant areas each interposed between the rows and making narrower a width of each vacant area than a narrowest width of a row among the rows of the first power-supply wiring pattern, and laying out a second signal wiring pattern electrically conductive to the first layer in two or more rows of the vacant areas on the second layer so that the second signal wiring pattern is not in contact with adjacent rows of the first power-supply wiring pattern on both sides.
Public/Granted literature
Information query
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