Invention Grant
US08614908B2 Bit line sense amplifier layout array, layout method, and apparatus having the same
有权
位线读出放大器布局阵列，布局方法和具有相同的装置
- Patent Title: Bit line sense amplifier layout array, layout method, and apparatus having the same
- Patent Title (中): 位线读出放大器布局阵列，布局方法和具有相同的装置
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Application No.: US13213508Application Date: 2011-08-19
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Publication No.: US08614908B2Publication Date: 2013-12-24
- Inventor: Jae Young Lee , Jong Hyun Choi , Hyang Ja Yang
- Applicant: Jae Young Lee , Jong Hyun Choi , Hyang Ja Yang
- Applicant Address: KR Suwon-Si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-Si
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2010-0081061 20100820
- Main IPC: G11C5/06
- IPC: G11C5/06
Abstract:
A bit line sense amplifier layout array includes N sense amplifier layout regions, which are arranged adjacent each other and have a sense amplifier, respectively. (N+1−i) bit lines and i complementary bit lines are arranged in an ith sense amplifier layout region among the sense amplifier layout regions. An ith bit line among the (N+1−i) bit lines and an ith complementary bit line among the i complementary bit lines are connected to a sense amplifier formed in the ith sense amplifier layout region. The values N and i are natural numbers and i>=1 and
Public/Granted literature
- US20120044734A1 BIT LINE SENSE AMPLIFIER LAYOUT ARRAY, LAYOUT METHOD, AND APPARATUS HAVING THE SAME Public/Granted day:2012-02-23
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