Invention Grant
- Patent Title: Phase locked loop circuit and receiver using the same
- Patent Title (中): 锁相环电路和接收机使用相同
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Application No.: US12553186Application Date: 2009-09-03
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Publication No.: US08615064B2Publication Date: 2013-12-24
- Inventor: Akihide Sai
- Applicant: Akihide Sai
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Turocy & Watson, LLP
- Priority: JP2009-024104 20090204
- Main IPC: H03D3/24
- IPC: H03D3/24

Abstract:
A phase locked loop circuit which obtains an output signal coincident in frequency and phase with a target signal which is acquired by multiplying the frequency of a reference signal by a ratio represented by the sum of a first fraction and a second fraction, the circuit includes a controlled oscillator including the same number of stages of annularly connected amplifiers as a number which is obtained by dividing, by 2, a least common multiple of a denominator of the first fraction, a denominator of the second fraction and 2, the same number of multiphase signals as the least common multiple being extractable from the controlled oscillator, the frequency of the multiphase signals being controlled by a digital control signal and an analog control signal, one of the multiphase signals being output as the output signal.
Public/Granted literature
- US20100195779A1 PHASE LOCKED LOOP CIRCUIT AND RECEIVER USING THE SAME Public/Granted day:2010-08-05
Information query
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