Invention Grant
- Patent Title: Switched interface stacked-die memory architecture
- Patent Title (中): 交换式接口堆叠式存储器架构
-
Application No.: US13595294Application Date: 2012-08-27
-
Publication No.: US08619481B2Publication Date: 2013-12-31
- Inventor: Joe M. Jeddeloh , Paul A. LaBerge
- Applicant: Joe M. Jeddeloh , Paul A. LaBerge
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
Public/Granted literature
- US20120320688A1 SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE Public/Granted day:2012-12-20
Information query