Invention Grant
US08619932B2 Signal transmission system with clock signal generator configured for generating clock signal having stepwise/smooth frequency transition and related signal transmission method thereof 有权
具有时钟信号发生器的信号传输系统被配置用于产生具有逐步/平滑频率转换的时钟信号及其相关的信号传输方法

  • Patent Title: Signal transmission system with clock signal generator configured for generating clock signal having stepwise/smooth frequency transition and related signal transmission method thereof
  • Patent Title (中): 具有时钟信号发生器的信号传输系统被配置用于产生具有逐步/平滑频率转换的时钟信号及其相关的信号传输方法
  • Application No.: US13109015
    Application Date: 2011-05-17
  • Publication No.: US08619932B2
    Publication Date: 2013-12-31
  • Inventor: Yu-Wei LinChih-Chien HungTsang-Yi Wu
  • Applicant: Yu-Wei LinChih-Chien HungTsang-Yi Wu
  • Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
  • Assignee: Mediatek Inc.
  • Current Assignee: Mediatek Inc.
  • Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
  • Agent Winston Hsu; Scott Margo
  • Main IPC: H04L7/00
  • IPC: H04L7/00
Signal transmission system with clock signal generator configured for generating clock signal having stepwise/smooth frequency transition and related signal transmission method thereof
Abstract:
A signal transmission system includes a first clock signal generator and a second clock signal generator. The first clock signal generator is configured for generating a first clock signal according to clock information derived from a transmitted signal, wherein the transmitted signal is changed in response to a frequency change of a second clock signal, and the first clock signal generator enters a frequency-unlocked state if the second clock signal has a frequency transition from a first frequency to a second frequency during a first time period. The second clock signal generator is configured for generating the second clock signal having the frequency transition from the first frequency to the second frequency during a second time period longer than the first time period such that the first clock signal generator stays in a frequency-locked state during the second time period.
Information query
Patent Agency Ranking
0/0