Invention Grant
US08623724B2 Method of manufacturing a semiconductor device including a capacitor electrically connected to a vertical pillar transistor
有权
制造半导体器件的方法,该半导体器件包括电连接到立柱晶体管的电容器
- Patent Title: Method of manufacturing a semiconductor device including a capacitor electrically connected to a vertical pillar transistor
- Patent Title (中): 制造半导体器件的方法,该半导体器件包括电连接到立柱晶体管的电容器
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Application No.: US13547318Application Date: 2012-07-12
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Publication No.: US08623724B2Publication Date: 2014-01-07
- Inventor: Hui-Jung Kim , Yong-Chul Oh , Jae-Man Yoon , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
- Applicant: Hui-Jung Kim , Yong-Chul Oh , Jae-Man Yoon , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
- Applicant Address: KR Suwon-Si, Gyeonggi-Do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-Si, Gyeonggi-Do
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2009-0025979 20090326
- Main IPC: H01L21/8242
- IPC: H01L21/8242

Abstract:
A semiconductor device includes a first transistor, a second transistor, an insulation interlayer pattern and a capacitor. The first transistor is formed in a first region of a substrate. The first transistor has a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar. The second transistor is formed in a second region of the substrate. The insulation interlayer pattern is formed on the first region and the second region to cover the second transistor and expose an upper surface of the pillar. The insulation interlayer pattern has an upper surface substantially higher than the upper surface of the pillar in the first region. The capacitor is formed on the impurity region in the upper portion of the pillar and is electrically connected to the impurity region.
Public/Granted literature
- US20120276698A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE Public/Granted day:2012-11-01
Information query
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