Invention Grant
US08623730B2 Method for fabricating silicon-on-insulator transistor with self-aligned borderless source/drain contacts
有权
用于制造具有自对准无边界源极/漏极触点的绝缘体上硅晶体管的方法
- Patent Title: Method for fabricating silicon-on-insulator transistor with self-aligned borderless source/drain contacts
- Patent Title (中): 用于制造具有自对准无边界源极/漏极触点的绝缘体上硅晶体管的方法
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Application No.: US13617866Application Date: 2012-09-14
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Publication No.: US08623730B2Publication Date: 2014-01-07
- Inventor: Susan S. Fan , Balasubramanian S. Haran , David V. Horak , Charles W. Koburger, III
- Applicant: Susan S. Fan , Balasubramanian S. Haran , David V. Horak , Charles W. Koburger, III
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Fleit Gibbons Gutman Bongini & Bianco PL
- Agent Stephen Bongini
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method is provided for fabricating a transistor. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.
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