Invention Grant
US08623742B2 Reduced STI loss for superior surface planarity of embedded stressors in densely packed semiconductor devices 有权
在密集封装的半导体器件中,降低了嵌入式应力源的表面平坦度的STI损耗

Reduced STI loss for superior surface planarity of embedded stressors in densely packed semiconductor devices
Abstract:
A reduction in material loss of trench isolation structures prior to forming a strain-inducing semiconductor alloy in transistor elements may result in superior device uniformity, for instance with respect to drive current and threshold voltage. To this end, at least one etch process using diluted hydrofluoric acid may be omitted when forming the shallow trench isolations, while at the same time providing a high degree of compatibility with conventional process strategies.
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