Invention Grant
US08623742B2 Reduced STI loss for superior surface planarity of embedded stressors in densely packed semiconductor devices
有权
在密集封装的半导体器件中,降低了嵌入式应力源的表面平坦度的STI损耗
- Patent Title: Reduced STI loss for superior surface planarity of embedded stressors in densely packed semiconductor devices
- Patent Title (中): 在密集封装的半导体器件中,降低了嵌入式应力源的表面平坦度的STI损耗
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Application No.: US13079341Application Date: 2011-04-04
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Publication No.: US08623742B2Publication Date: 2014-01-07
- Inventor: Stephan Kronholz , Matthias Kessler , Thomas Feudel
- Applicant: Stephan Kronholz , Matthias Kessler , Thomas Feudel
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams, Morgan & Amerson, P.C.
- Priority: DE102010028464 20100430
- Main IPC: H01L21/76
- IPC: H01L21/76

Abstract:
A reduction in material loss of trench isolation structures prior to forming a strain-inducing semiconductor alloy in transistor elements may result in superior device uniformity, for instance with respect to drive current and threshold voltage. To this end, at least one etch process using diluted hydrofluoric acid may be omitted when forming the shallow trench isolations, while at the same time providing a high degree of compatibility with conventional process strategies.
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