Invention Grant
- Patent Title: Contact integration for three-dimensional stacking semiconductor devices
- Patent Title (中): 触点集成三维堆叠半导体器件
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Application No.: US12969975Application Date: 2010-12-16
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Publication No.: US08624300B2Publication Date: 2014-01-07
- Inventor: Sanh D. Tang , John Zahurak , Shane Trapp , Krishna K. Parat
- Applicant: Sanh D. Tang , John Zahurak , Shane Trapp , Krishna K. Parat
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Cool Patent, P. C.
- Main IPC: H01L23/52
- IPC: H01L23/52
Abstract:
Briefly, in accordance with one or more embodiments, multilayer memory device, comprising a lower deck and an upper deck disposed on the lower deck, the decks comprising one or more memory cells coupled via one or more contacts. An isolation layer is disposed between the upper deck, and one or more contacts are formed between the upper deck and the lower deck to couple one or more of the contact lines of the upper deck with one or more contact lines of the lower deck.
Public/Granted literature
- US20120153357A1 CONTACT INTEGRATION FOR THREE-DIMENSIONAL STACKING SEMICONDUCTOR DEVICES Public/Granted day:2012-06-21
Information query
IPC分类:
