Invention Grant
- Patent Title: Exclusion zone for stress-sensitive circuit design
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Application No.: US11324967Application Date: 2006-01-03
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Publication No.: US08624346B2Publication Date: 2014-01-07
- Inventor: Chao-Yuan Su , Chung-Yi Lin
- Applicant: Chao-Yuan Su , Chung-Yi Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/29
- IPC: H01L23/29

Abstract:
A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.
Public/Granted literature
- US20070090547A1 Exclusion zone for stress-sensitive circuit design Public/Granted day:2007-04-26
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