Invention Grant
- Patent Title: Semiconductor device having chip crack detection structure
- Patent Title (中): 具有芯片裂纹检测结构的半导体器件
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Application No.: US13461627Application Date: 2012-05-01
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Publication No.: US08624401B2Publication Date: 2014-01-07
- Inventor: Toru Ishikawa
- Applicant: Toru Ishikawa
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2011-111673 20110518
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40

Abstract:
A device includes a semiconductor substrate, a first penetration electrode and a plurality of second penetration electrodes each penetrating the semiconductor substrate, a first terminal and a plurality of second terminals formed on a one side of the substrate, and a third terminal and a plurality of fourth terminals formed on an opposite side of the substrate. Each of the first and third terminals is vertically aligned with and electrically connected to first penetration electrode. Each of the second terminals is vertically aligned with an associated one of the second penetration electrodes and electrically connected to another one of the second penetration terminals that is not vertically aligned with the associated second terminal. Each of fourth terminals is vertically aligned with and electrically connected to an associated one of the second penetration electrodes.
Public/Granted literature
- US20120292759A1 SEMICONDUCTOR DEVICE HAVING CHIP CRACK DETECTION STRUCTURE Public/Granted day:2012-11-22
Information query
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