Invention Grant
- Patent Title: 3D IC structure and method
- Patent Title (中): 3D IC结构和方法
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Application No.: US13295312Application Date: 2011-11-14
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Publication No.: US08624626B2Publication Date: 2014-01-07
- Inventor: Shyh-An Chi
- Applicant: Shyh-An Chi
- Applicant Address: TW Hsin-chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-chu
- Agency: Duane Morris LLP
- Agent Steven E. Koffs
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/50

Abstract:
An apparatus comprises a first integrated circuit (IC) die, and a second IC die stacked on the first IC die. The first and second IC dies are operational independently of each other. Each respective one of the first and second IC dies has: at least one circuit for performing a function; an operation block coupled to selectively disconnect the circuit from power; and an output enable block coupled to selectively connect the circuit to at least one data bus.
Public/Granted literature
- US20130120021A1 3D IC STRUCTURE AND METHOD Public/Granted day:2013-05-16
Information query
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