Invention Grant
- Patent Title: PLL dual edge lock detector
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Application No.: US13950427Application Date: 2013-07-25
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Publication No.: US08624642B2Publication Date: 2014-01-07
- Inventor: Xiaoyue Wang , Shafiq M. Jamal
- Applicant: Marvell World Trade Ltd.
- Applicant Address: BB St. Michael
- Assignee: Marvell World Trade Ltd.
- Current Assignee: Marvell World Trade Ltd.
- Current Assignee Address: BB St. Michael
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.
Public/Granted literature
- US20130307596A1 PLL DUAL EDGE LOCK DETECTOR Public/Granted day:2013-11-21
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