An interleave address generation circuit includes a plurality of linear feedback shift registers operable to generate addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis. The interleave address generation circuit is operable to generate the lane addresses for each subword and the linear feedback registers configured to generate circulant addresses and sub-circulant address to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain.